Integrated circuits including logic devices and interface circuits based upon metal-oxide-semiconductor field-effect transistors (MOSFETs) are typically fabricated using a standard complimentary-metal-oxide-semiconductor (CMOS) process flows, involving the formation and patterning of conducting, semiconducting and dielectric materials. The composition of these materials, as well as the composition and concentration of processing reagents, and temperature used in such a CMOS process flow are stringently controlled for each operation to ensure the resultant MOSFETs will function properly. For many applications it is desirable to include non-volatile memory devices based upon FETs including charge-trapping gate stacks in the integrated circuit. Charge-trapping gate stack formation involves the formation of a nitride or oxynitride charge-trapping layer sandwiched between two dielectric or oxide layers typically fabricated using materials and processes that differ significantly from those of the standard CMOS process flow, and which can detrimentally impact or be impacted by the fabrication of the MOSFETs. In particular, forming a gate oxide or dielectric of a MOSFET can significantly degrade performance of a previously formed charge-trapping gate stack by altering a thickness or composition of the charge-trapping layer.